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www.azmicrotek.com 1630 s stapley dr, suite 127 +1 - 480- 962- 5881 mesa, az 85204 usa request a sample mar 2013 , rev 2 .2 d escription the azp63 is a sine wave/cmos to lvpecl buffer/ translator optimized for very low phase noise ( - 165dbc/hz). it is particularly useful in converting crystal or saw based oscillators into lvpecl outputs for greater than 1ghz of bandwidth. for lower power consumption and reduced bandwidth, refer to the azp5x family. the azp63 is one of a family of parts that provide options of fi xed 1, fixed 2 and selectable 1, 2 modes as well as active high enable or active low enable to oscillator designers. refer to table 2 for the comparison of parts within the azp5x and azp63 family. b lock d iagram pull-up en_sel en (pu,pd) d v dd /2 1,2 q q gnd v dd pull-down pu div_sel pd r bias f eatures ? lvpecl outputs optimized for very low phase noise ( - 165dbc/hz) ? high bandwidth, > 1ghz ? selectable 1, 2 output ? selectable enable logic ? 3.0v to 3.6v operation p ackage a vailability ? available in die ? son8 ? green/rohs compliant/pb - free a pplications ? pecl clock sources ? crystal or saw based oscillators with lvpecl output az p63 low phase noise sine wave / cmos to lvpecl buffer / translator order number package marking azp63qg 1 son8 e 2 1 tape & reel - add 'r1' at end of order number for 7in (1k parts), 'r2' (2.5k) for 13in 2 see www.azmicrotek.com for date code format www.azmicrotek.com
arizona microtek, inc. az p63 low phase noise sine wave cmos to lvpecl buffer/ translator www.azmicrotek.com +1 - 480- 962- 5881 2 request a sample mar 2013 , rev 2.2 p in d escription and c onfiguration table 1 - pin description pin name type function 1 q output lvpecl output 2 q output lvpecl output 3 en input enable 4 gnd power negative supply 5 ? d input sine or cmos input 6 en_sel input enable select 7 div_sel input divide select 8 v dd power positive supply 1 v dd 3 2 gnd e 4 8 6 7 5 q en q div_sel d en_sel figure 1 - p in configuration
arizona microtek, inc. az p63 low phase noise sine wave cmos to lvpecl buffer/ translator www.azmicrotek.com +1 - 480- 962- 5881 3 request a sample mar 2013 , rev 2.2 e ngineering n otes f unctionality the azp63 is one of a family of parts that provide options of fixed 1, fixed 2 and selectable 1, 2 modes as well as active high enable or active low enable to oscillator designers. table 2 details the differences between the parts to assist designers in selecting the optimal part for their design. table 3 lists the specific azp63 functional operation. figure 2 plots the s - parameters of the ? d input. s - parameter and ibis model files for the azp63 are also available for download . table 2 - azp51 - 54 & azp63 family part number divide ratio en logic en pull - up/pull - down bandwidth azp51 1 active high pull - up > 800mhz azp52 2 active high pull - up > 800mhz azp53 selectable 1 or 2 selectable selectable > 800mhz azp54 1 active low pull - down > 800mhz azp63 selectable 1 or 2 selectable selectable 1ghz table 3 ? azp63 functional operation , 1 mode inputs outputs part number en_sel en ? d q ? q azp63 high, nc 1 low, nc 1 low low high high high low high x 2 z 3 z 3 low high, nc 1 low low high high high low low x 2 z 3 z 3 div_sel divide ratio low, nc 1 1 high 2 1 not connected 2 don't care 3 tri - state
arizona microtek, inc. az p63 low phase noise sine wave cmos to lvpecl buffer/ translator www.azmicrotek.com +1 - 480- 962- 5881 4 request a sample mar 2013 , rev 2.2 figure 2 - s11 , parameters, ? d input i nput t ermination the ? d input bias is v dd /2 fed through an internal 10k ? resistor. for clock applications, an input signal of at least 750mv pp ensures the azp63 meets ac specifications. the input should also be ac coupled to maintain a 50% duty cycle on the outputs. the input can be driven to any voltage between 0v and v dd wit hout damage or waveform degradation. d v dd /2 10k? input signal a/r figure 3 - input termination
arizona microtek, inc. az p63 low phase noise sine wave cmos to lvpecl buffer/ translator www.azmicrotek.com +1 - 480- 962- 5881 5 request a sample mar 2013 , rev 2.2 o utput t ermination t echniques the lvpecl compatible output stage of the azp63 uses a current drive topology to maximize switching speed as illustrated below in figure 4 . two curren t source pmos transistors (m1 - m2) feed the output pins. m5 is an nmos current source which is switched by m3 and m4. when m4 is on, m5 takes current from m2. this produces an output current of 5.1ma (low output state). m3 is off, and the entire 21.1ma flow s through the output pin. the associated output voltage swings match lvpecl levels when external 50 ? resistors terminate the outputs. both q and q should always be terminated identically to avoid waveform distortion and circulating current caus ed by unsymmetrical loads. this rule should be followed even if only one output is in use. v dd (+3.3 v) v bp m1 m2 m3 m4 d v bn m5 21.1ma 21.1ma 16ma v tt = v dd - 2.0v q q 50? 50? 21.1ma - high 5.1ma - low external circuitry output stage figure 4 - typical output termination d ual s upply lvpecl o utput t ermination the standard lvpecl loads are a pai r of 50 ? resistors connected between the outputs and v dd - 2.0v ( figure 4 ). the resistors provide both the dc and the ac loads, assuming 50 ? interconnect. if an additional supply is available within the application, a four resistor termination configuration is possible ( figure 5 ).
arizona microtek, inc. az p63 low phase noise sine wave cmos to lvpecl buffer/ translator www.azmicrotek.com +1 - 480- 962- 5881 6 request a sample mar 2013 , rev 2.2 v dd (+ 3 . 3 v ) v bp m 1 m2 m3 m4 d v bn m5 21.1ma 21.1ma 16ma q q 82? 82? 21.1ma - high 5.1ma - low external circuitry output stage 130? 130? v dd (+3.3 v) figure 5 - dual supply output termination t hree r esistor t ermination another termination variant eliminates the need for the additional supply ( figure 6 ). alternately three resistors and one capacitor accomplish the same termination and reduce power consumption. v dd (+ 3 . 3 v ) v bp m 1 m 2 m 3 m 4 d v bn m 5 21 . 1 ma 21 . 1 ma 16 ma q q 50 ? 50 ? 21 . 1 ma - high 5 . 1 ma - low external circuitry output stage 50 ? 0 . 01 f figure 6 - three resistor termination
arizona microtek, inc. az p63 low phase noise sine wave cmos to lvpecl buffer/ translator www.azmicrotek.com +1 - 480- 962- 5881 7 request a sample mar 2013 , rev 2.2 e valuation b oard (ebp53) arizona microtek?s evaluation board ebp53 provides the most convenient way to test and prototype azp63 series circuits. built for the azp53q 1.5x1.0 mm package, it is designed to support both dual and single supply operation. dual supply operation (v dd =+2.0v, v ss = - 1.3v) enables direct coupling to 50 ? time domain test equipment ( figure 7 ). v dd (+2.0 v) v bp m1 m2 m3 m4 d v bn m5 21.1ma 21.1ma 16ma q q 50? 50? 21.1ma - high 5.1ma - low test equipment terminations output stage v ss (-1.3 v) figure 7 - split supply lvpecl output termination ac t ermination clock applications or phase noise/frequency domain testing scenarios typically require ac coupling. figure 8 below shows the ac coupling technique. the 200 ? resistors form the required dc loads, and the 50 ? resistors provide the ac termination. the parallel combination of the 200 ? and 50 ? resistors results in a net 40 ? ac load termination. in many cases this will work well. if necessary, the 50 ? resistors can be increased to about 56 ? . alternately, bias tees combined with current setting resistors will eliminate the lowered ac load impedance. the 50 ? resistors are typic ally connected to ground but can be connected to the bias level needed by the succeeding stage.
arizona microtek, inc. az p63 low phase noise sine wave cmos to lvpecl buffer/ translator www.azmicrotek.com +1 - 480- 962- 5881 8 request a sample mar 2013 , rev 2.2 v dd (+ 3 . 3 v ) v bp m 1 m 2 m 3 m 4 d v bn m 5 21 . 1 ma 21 . 1 ma 16 ma q q 200 ? 200 ? 21 . 1 ma - high 5 . 1 ma - low external circuitry output stage 0 . 01 f 0 . 01 f 50 ? 50 ? gnd or v t figure 8 - ac termination p erformance data table 4 - absolute maximum ratings absolute maximum ratings are those values beyond which device life may be impaired. symbol characteristic rating unit v dd power supply 0 to +5.5 v v i input voltage - 0.5 to v dd + 0.5 v t a operating temperature range - 40 to +85 c t stg storage temperature range - 65 to +150 c esd hbm human body model 2000 v esd mm machine model 100 v esd cdm charged device model 2000 v
arizona microtek, inc. az p63 low phase noise sine wave cmos to lvpecl buffer/ translator www.azmicrotek.com +1 - 480- 962- 5881 9 request a sample mar 2013 , rev 2.2 table 5 - dc characteristics dc characteristics (v dd = 3.0v to 3.6v unless otherwise specified, t a = - 40 to 85 c) symbol characteristic conditions min typ max unit v oh output high voltage 1 -40 c v dd = 3.3v 2.2 2.45 v 25 c 2.2 2.45 85 c 2.2 2.45 v ol output low voltage 1 -40 c v dd = 3.3v 1.4 1.68 v 25 c 1.4 1.68 85 c 1.4 1.68 i z output leakage current, tri - state 2 en=disable -10 10 a v ih high level input voltage en_sel 2 v div_sel v il low level input voltage en 0.8 v i pu pullup current en_sel 2.2 a i pd pulldown current div_sel - 2.2 a i p pullup/pulldown current en 2.2 a r bias bias resistor ? d input to internal v dd /2 reference 10k i dd power supply current 64 70 ma i ddsw power supply current fast switching 1,3,4 input freq >1ghz 88 ma i ddz power supply current outputs tri - state 1 ? d input v il en=disables 8 ma 1 specified with outputs terminated through 50 ? resistors to v dd - 2v or thevenin equivalent. 2 measured at q / ? q pins. 3 includes load current through external 50 q resistors to v dd - 2v 4 current measured in 1 mode, ? d and q / ? q pins switching at 1000mhz
arizona microtek, inc. az p63 low phase noise sine wave cmos to lvpecl buffer/ translator www.azmicrotek.com +1 - 480- 962- 5881 10 request a sample mar 2013 , rev 2.2 table 6 - ac characteristics ac characteristics (v dd = 3.0v to 3.6v, t a = - 40 to 85 c) ac specifications guaranteed by design symbol characteristic min typ max unit t r / t f output rise/fall 1,2 80 250 ps (20% - 80%) f max maximum input frequency - sine wave 2 mhz 1 1000 2 1500 v inmax maximum recommended input signal v dd vpp v inmin minimum recommended input signal 0.2 vpp t plh propagation delay 938 1614 ps t phl propagation delay 938 1614 ps j rms rms jitter: 12khz - 20mhz, 155mhz center freq 36 fs n p phase noise 1,2 - 1mhz offset - 165 dbc/hz 1 specified with outputs terminated through 50w resistors to v cc - 2v or thevenin equivalent. 2 1.5 v p - p sine wave input, ac coupled to ? d pin.
arizona microtek, inc. az p63 low phase noise sine wave cmos to lvpecl buffer/ translator www.azmicrotek.com +1 - 480- 962- 5881 11 request a sample mar 2013 , rev 2.2 p ackage d iagram son8 (1.5x1.0 x0.4 mm) green/rohs compliant/pb - free msl =1
arizona microtek, inc. az p63 low phase noise sine wave cmos to lvpecl buffer/ translator www.azmicrotek.com +1 - 480- 962- 5881 12 request a sample mar 2013 , rev 2.2 die size 7 5 4 x 354 pad size 52 . 1 octa g onal die coordina t es (cent e r 0 , 0) pad name x coordinate (m) y coordinate (m) d - 273.875 - 106.575 en_sel - 140.35 0 - 106.65 0 div_sel - 43.625 - 106.65 0 vdd 302.875 - 20.45 0 q 170.925 105.725 qn 72.55 0 105.725 en - 175.3 00 106 .000 gnd - 296.35 0 72.325 d ie s pecifications arizona microtek, inc. reserves the right to change circuitry and specifications at any time without prior notice. arizona microtek, inc. makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does arizona microtek, inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. arizona microtek, inc. does not convey any license rights nor the rights of others. arizona microtek, inc. products are not designed, intended or authorized for use as components in systems intended to support or sustain life, or for any other application in which the failure of the arizona microtek, inc. product could create a situation where personal injury or death may occur. should buyer purchase or use arizona microtek, inc. products for any such unintended or unauthorized application, buyer shall indemnify and hold arizona microtek, inc. and its officers, employe es, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthor ized use, even if such claim alleges that arizona microtek, inc. was negligent regarding the design or manufacture of the part.

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